A programmable logic device (PLD), like FPGA (Field-Programmable Gate Array), is widely used as what can be reconfigured circuit configuration. Applicants or inventors have researched and developed “memory-based programmable logic device (MPLD)” (registered trademark) that realizes circuit configuration by using memory cell units. For example, the MPLD is described in Patent Document 1 below. The MPLD is constituted by MLUTs (Multi Look-Up-Table) that has all functions of memorize, LUT (Look-Up-Table), and switch. The MPLD realizes almost the same function of FPGA by being arrayed MLUTs which are mutually connected.
Further, the MPLD is different from FPGA which has switching circuits only for connecting memory cell units because the MPLD is a device whose a logic region and a connecting region have flexibility by using MLUTs as both a logic element and a connecting element.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2009-194676
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2008-166771